Design the first step, set goals

　　In IC design, the most important step is specification development. This step is like before designing a building, first decide how many rooms and bathrooms you want, what building regulations need to be complied with, and design after all the functions are determined, so that you don’t need to spend extra time on subsequent revisions. IC design also needs to go through similar steps to ensure that the designed chip will not have any errors.

　　The first step in formulating specifications is to determine the purpose and performance of the IC, and to set the general direction. Then check which protocols must be complied with. For example, the chip of the wireless network card must conform to IEEE 802.11 and other specifications. Otherwise, the chip will not be compatible with the products on the market, making it unable to connect with other devices. The last step is to establish the implementation method of this IC, assign different functions into different units, and establish the method of connection between different units, so as to complete the formulation of the specification.

　　After designing the specifications, the next step is to design the details of the chip. This step is like initially writing down the planning of the building, and drawing the overall outline to facilitate subsequent drawing. In an IC chip, the circuit is described using a hardware description language (HDL). Commonly used HDLs include Verilog, VHDL, etc., and the functions of an IC can be easily expressed through codes. The next step is to check the correctness of the program function and continue to modify it until it meets the desired function.
　　
　　▲ Verilog example of 32 bits adder.

　　With computers, things are easier

　　After having a complete plan, the next step is to draw a planar design blueprint. In IC design, the step of logic synthesis is to put the unmistakable HDL code into the electronic design automation tool (EDA tool), let the computer convert the HDL code into a logic circuit, and generate the following circuit diagram. After that, repeatedly determine whether the logic gate design meets the specification and revise it until the function is correct.
　　
　　▲ The result after the synthesis of the control unit.

　　Finally, put the synthesized code into another EDA tool for circuit layout and routing (Place And Route). After continuous testing, the following circuit diagram will be formed. In the picture, different colors such as blue, red, green, and yellow can be seen, and each different color represents a mask. As for how to use the mask?
　　
　　▲ The commonly used calculation chip - FFT chip, completes the result of circuit layout and winding.

　　Layers of photomasks stack up a chip

　　First of all, it is already known that one IC will produce multiple masks. These masks have different layers, and each layer has its own tasks. The figure below is a simple example of a photomask, taking CMOS, the most basic component in an integrated circuit, as an example. combined to form CMOS. As for what is Metal Oxide Semiconductor (MOS)? This kind of component widely used in chips is more difficult to explain, and it is also more difficult for general readers to understand, so I won't go into details here.

　　In the figure below, the left side is the circuit diagram formed after circuit layout and winding. It is already known that each color represents a photomask. On the right is how each mask is spread out. The production is to start from the bottom layer, follow the method mentioned in the previous IC chip production, and make it layer by layer, and finally the desired chip will be produced.
　　
　　At this point, you should have a preliminary understanding of IC design. Overall, it is clear that IC design is a very complicated profession. Thanks to the maturity of computer-aided software, IC design can be accelerated. IC design factories rely heavily on the wisdom of engineers. Each step described here has its own specialized knowledge, and can be independently formed into multiple professional courses. For example, writing a hardware description language is not simply a matter of being familiar with programming languages , It is also necessary to understand how the logic circuit works, how to convert the required algorithm into a program, and how the synthesis software converts the program into a logic gate.

       In semiconductor news, fabs marked by size are always mentioned, such as 8-inch or 12-inch fabs. However, what is the so-called wafer? What part does 8 inches refer to? How difficult is it to produce large-sized wafers? The following will gradually introduce the most important foundation of semiconductors - what exactly is a "wafer".

　　Wafer is the basis for manufacturing various computer chips. We can compare chip manufacturing to building a house with Lego blocks, and by stacking layers one after another, we can complete the shape we want (that is, all kinds of chips). However, if there is no good foundation, the house built will be crooked and unsatisfactory. In order to make a perfect house, a stable substrate is needed. For chip manufacturing, this substrate is the wafer described next.

　　
　　(Souse: Flickr/Jonathan Stewart CC BY 2.0)

　　First of all, let’s recall that when we were playing with Lego blocks when we were young, there would be small round protrusions on the surface of the blocks. With this structure, we can stack two blocks together firmly without using glue . Chip manufacturing also uses a similar method to fix the subsequently added atoms and the substrate together. Therefore, we need to look for a substrate with a neat surface to meet the conditions required for subsequent manufacturing.

　　In solid materials, there is a special crystal structure - monocrystalline (Monocrystalline). It has the property that atoms are packed close together, one behind the other, to form a flat atomic surface. Therefore, using a single crystal to make a wafer can meet the above requirements. However, how to produce such a material mainly involves two steps, namely purification and crystal pulling, after which such a material can be completed.

　　How to Make Single Crystal Wafers

　　Purification is divided into two stages. The first step is metallurgical purification. This process is mainly to add carbon to convert silicon oxide into silicon with a purity of more than 98% in a redox manner. Most of the refining of metals, such as iron or copper, use this method to obtain metals of sufficient purity. However, 98% is still not enough for chip manufacturing and needs to be further improved. Therefore, the Siemens process (Siemens process) will be further used for purification, so that high-purity polysilicon required for semiconductor manufacturing processes will be obtained.

　　
　　▲ Silicon column manufacturing process (Source: Wikipedia)

　　Next, is the step of pulling the crystal. First, the high-purity polysilicon obtained above is melted to form liquid silicon. Afterwards, the single crystal silicon seed (seed) is in contact with the surface of the liquid, and slowly pulled up while rotating. As for why single-crystal silicon seeds are needed, it is because the arrangement of silicon atoms is the same as that of people queuing up, and they need to be arranged first to let subsequent people know how to arrange them correctly. Finally, after the silicon atoms leaving the liquid surface are solidified, the neatly arranged single crystal silicon pillars are completed.

　　
　　▲ Monocrystalline silicon column (Souse: Wikipedia)

　　However, what do 8 inches and 12 inches represent? He was referring to the crystal column that we produce, the part that looks like the shaft of a pencil, the diameter after the surface has been treated and sliced into thin discs. As for the difficulty in manufacturing large-size wafers? As mentioned earlier, the production process of crystal pillars is like making cotton candy, forming while rotating. If you have ever made marshmallows, you should know that it is quite difficult to make large and solid marshmallows, and the process of pulling crystals is the same. The speed of spinning and pulling up and the control of temperature will affect the quality of crystal pillars. Therefore, the larger the size, the higher the speed and temperature requirements for crystal pulling, so it is more difficult to make high-quality 12-inch wafers than 8-inch wafers.

　　However, a whole silicon column cannot be used as a substrate for chip manufacturing. In order to produce silicon wafers piece by piece, it is necessary to cut the silicon column horizontally into wafers with a diamond knife, and then polish the wafers to form chips. Fabricate the required silicon wafers. After so many steps, the manufacture of the chip substrate is complete, and the next step is the step of stacking houses, that is, chip manufacturing. As for how to make the chip?

　　After introducing what a silicon wafer is, at the same time, I also know that manufacturing IC chips is like building a house with Lego blocks. By stacking layers one after another, you can create your desired shape. However, there are quite a few steps in building a house, and so is IC manufacturing. What are the steps in making an IC? This article will introduce the process of IC chip manufacturing.

　　Before we start, we need to know what an IC chip is. IC, the full name of Integrated Circuit (Integrated Circuit), can be known from its name that it combines the designed circuits in a stacked manner. By this method, we can reduce the area required to connect the circuits. The figure below is a 3D diagram of an IC circuit. It can be seen from the figure that its structure is like the beams and columns of a house, stacked layer by layer, which is why IC manufacturing is compared to building a house.

　　
　　▲ 3D cross-sectional view of an IC chip. (Source: Wikipedia)

　　From the 3D cross-sectional view of the IC chip in the above picture, the dark blue part at the bottom is the wafer introduced in the previous article. From this picture, we can more clearly know how important the role of the wafer substrate is in the chip. As for the red and khaki part, it is the place to be completed during IC production.

　　First of all, the red part can be compared to the lobby on the first floor of a tall building. The lobby on the first floor is the portal of a house, and all the access and exits are here. It usually has more functions under the control of traffic. Therefore, compared with other floors, it will be more complicated to construct and require more steps. In an IC circuit, this hall is the logic gate layer, which is the most important part of the entire IC. By combining various logic gates, a fully functional IC chip is completed.

　　The yellow part looks like a normal floor. Compared with the first floor, there will not be too complicated structure, and there will not be too many changes in the construction of each floor. The purpose of this layer is to connect the logic gates of the red part together. The reason why so many layers are needed is because there are too many lines to be connected together. If a single layer cannot accommodate all the lines, it is necessary to stack several layers to achieve this goal. Among them, the lines of different layers will be connected up and down to meet the needs of wiring.

　　Layered construction, layer by layer architecture

　　After knowing the structure of the IC, the next step is to introduce how to make it. Just imagine, if we want to make fine drawings with paint spray cans, we need to cut out the cover board of the graphics and cover them on the paper. Then spray the paint evenly on the paper, and after the paint dries, remove the mask. After repeating this step continuously, neat and complex graphics can be completed. Manufacturing ICs is done in a similar way, layer by layer by masking.

　　When making an IC, it can be simply divided into the above four steps. Although there are differences in manufacturing steps and materials used in actual manufacturing, they generally adopt similar principles. This process is slightly different from painting with paint. IC manufacturing is to paint first and then cover, while painting with paint is to cover first and then paint. Each process is described below.

　　Metal sputtering: Sprinkle the metal material to be used evenly on the wafer to form a thin film.

　　Coating photoresist: First put the photoresist material on the wafer, pass through the mask (the principle of the photomask will be explained next time), and hit the light beam on the unnecessary part to destroy the structure of the photoresist material. Next, the damaged material is washed away with chemicals.

　　Etching technology: The silicon wafer that is not protected by photoresist is etched with ion beam.

　　Photoresist removal: Use photoresist remover to dissolve the remaining photoresist, thus completing a process.

　　In the end, many IC chips will be completed on a whole wafer, and then the completed square IC chips can be cut out and sent to a packaging factory for packaging. As for what is a packaging factory? I will explain it later.
　　
　　▲ Comparison of wafers of various sizes. (Source: Wikipedia)

　　Samsung and TSMC are very active in the advanced semiconductor manufacturing process. Both of them want to seize the opportunity in the foundry to win orders. It has almost become a battle between 14nm and 16nm. However, the two 14nm and 16nm What is the meaning of the number, and which part does it refer to? And what benefits and problems will it bring in the future after shrinking the manufacturing process? Below we will briefly explain the nano-process.

　　How tiny are nanometers?

　　Before we get started, it's important to understand what exactly nano means. Mathematically, a nanometer is 0.000000001 meter, but this is a pretty poor example, after all, we only see a lot of zeros after the decimal point, but have no actual feeling. If you compare it with the thickness of your nails, it may be more obvious.

　　If you actually measure it with a ruler, you can know that the thickness of the nail is about 0.0001 meters (0.1 mm), that is to say, try to cut the side of a piece of nail into 100,000 lines, and each line is equivalent to about 1 nanometer. This can slightly imagine how tiny 1 nanometer is.

　　After knowing how small the nanometer is, you must also understand the purpose of shrinking the process. The main purpose of shrinking the transistor is to pack more transistors into a smaller chip, so that the chip will not become smaller due to technological improvement. Second, it can increase the computing efficiency of the processor; third, reducing the size can also reduce power consumption; finally, after the chip is reduced in size, it is easier to plug into mobile devices to meet the needs of future thinning and lightening.

　　Let’s come back to explore what the nano-process is. Taking 14nm as an example, the process means that the wires in the chip can be as small as 14nm. The figure below shows the appearance of a traditional transistor as an example. The main purpose of reducing the transistor is to reduce power consumption, but which part should be reduced to achieve this goal? The L in the lower left figure is the part we expect to shrink. By reducing the length of the gate, the current can use a shorter path from the Drain terminal to the Source terminal (if you are interested, you can use Google to search for MOSFETs, and there will be more detailed explanations).

　　(Source: www.slideshare.net)

　　In addition, computers operate on 0 and 1. How can transistors be used for this purpose? The method is to judge whether the transistor has current flow. When the voltage supply is made at the Gate terminal (green square), the current will flow from the Drain terminal to the Source terminal. If there is no supply voltage, the current will not flow, so that 1 and 0 can be represented. (As for why 0 and 1 are used to make judgments, if you are interested, you can go to Chabling Algebra, we use this method to make a computer)

　　Size reduction has its physical limits

　　However, the manufacturing process cannot be reduced indefinitely. When we shrink the transistor to about 20 nanometers, we will encounter problems in quantum physics, which will cause the transistor to have leakage, which will offset the benefits obtained when reducing L. As an improvement method, the concept of FinFET (Tri-Gate) is introduced, as shown in the upper right picture. In Intel's previous explanation, it can be known that by introducing this technology, the leakage caused by physical phenomena can be reduced.

　　
　　(Source: www.slideshare.net)

　　More importantly, this method can increase the contact area between the Gate end and the lower layer. In the traditional method (upper left picture), the contact surface has only one plane, but after using FinFET (Tri-Gate) technology, the contact surface will become three-dimensional, and the contact area can be easily increased, so that the same contact can be maintained. The area makes the Source-Drain end smaller, which is of great help in reducing the size.

　　Finally, it is why some people say that major manufacturers will face severe challenges when entering the 10nm process. The main reason is that the size of an atom is about 0.1nm. In the case of 10nm, a line has less than 100 atoms. It is very difficult to manufacture, and as long as there is an atomic defect, such as atoms falling out or impurities during the manufacturing process, unknown phenomena will occur and affect the yield of the product.

　　If you can't imagine the difficulty, you can do a small experiment. Use 100 small beads to form a 10×10 square on the table, and cut a piece of paper to cover the beads, then use a small brush to brush off the beads next to it, and finally make it a 10×5 rectangle. In this way, we can know the difficulties faced by major factories and how difficult it is to achieve this goal.

　　As Samsung and TSMC will complete the mass production of 14nm and 16nm FinFETs in the near future, both of them want to compete for Apple's next-generation iPhone chip foundry, we will see a very exciting business competition, and will also get more power-saving , Thin and light mobile phones, thanks to the benefits brought by Moore's Law.

　　After a long process, from design to manufacture, an IC chip is finally obtained. However, a chip is quite small and thin, and can be easily damaged by scratches if it is not protected externally. In addition, because of the small size of the chip, it is not easy to manually place it on the circuit board without a larger size housing. Therefore, the next part of this article will describe the packaging.

　　There are two common packages at present, one is the black DIP package that looks like a centipede, which is common in electric toys, and the other is the BGA package that is common when buying boxed CPUs. As for other packaging methods, there are PGA (Pin Grid Array; Pin Grid Array) used by early CPUs or an improved version of DIP QFP (Plastic Quad Flat Package). Because there are too many packaging methods, DIP and BGA packaging will be introduced below.

　　Traditional packaging, enduring

　　The first thing to introduce is the Dual Inline Package (DIP). From the figure below, you can see that the IC chip using this package looks like a black centipede under the double-row pins, which is impressive. The encapsulation method is the earliest adopted IC encapsulation technology, which has the advantage of low cost and is suitable for small chips that do not require too many wires. However, because most of them are made of plastic, the heat dissipation effect is poor, which cannot meet the requirements of current high-speed chips. Therefore, most of the chips that use this package are long-lasting chips, such as the OP741 in the figure below, or IC chips that do not require so much operating speed and have smaller chips and fewer holes.

　　▲ The IC chip on the left is OP741, which is a common voltage amplifier. The picture on the right is its cross-sectional view. This package uses gold wires to connect the chip to the metal pin (Leadframe). (Source: Wikipedia on the left, Wikipedia on the right)

　　As for the Ball Grid Array (BGA) package, compared with DIP, the package is smaller in size and can be easily put into smaller devices. In addition, because the pins are under the chip, it can accommodate more metal pins than DIP

　　Quite suitable for chips that require more contacts. However, the cost of this packaging method is high and the connection method is relatively complicated, so it is mostly used in products with high unit prices.　　

　　▲ The picture on the left shows a chip packaged in BGA. The picture on the right is a schematic diagram of a BGA using a flip-chip package. (Source: Wikipedia on the left)
　　With the rise of mobile devices, new technologies are on the stage

　　However, using the above encapsulation methods consumes a considerable volume. Like the current mobile devices, wearable devices, etc., quite a variety of components are required. If each component is packaged independently, the combination will consume a very large space. Therefore, there are currently two methods to meet the requirements of reducing the size, namely SoC ( System On Chip) and SiP (System In Packet).

　　When smartphones were just emerging, the term SoC could be found in major financial magazines, but what exactly is SoC? Simply put, it is to integrate ICs with different functions into one chip. With this method, not only can the size be reduced, but also the distance between different ICs can be reduced, and the calculation speed of the chip can be improved. As for the manufacturing method, in the IC design stage, various ICs are put together, and then a photomask is made through the design process introduced earlier.

　　However, SoC does not only have advantages, to design a SoC requires quite a lot of technical cooperation. When the IC chips are individually packaged, each has external protection of the package, and the distance between the IC and the IC is relatively long, so there is less chance of mutual interference. But when all the ICs are packaged together, the nightmare begins. IC design factories need to change from simply designing ICs to understanding and integrating ICs with various functions, increasing the workload of engineers. In addition, there will be many situations, such as the high-frequency signal of the communication chip may affect other functional ICs and so on.

　　In addition, SoC also needs to obtain IP (intellectual property) authorization from other manufacturers in order to put components designed by others into SoC. Because the making of SoC needs to obtain the design details of the whole IC to make a complete photomask, which also increases the design cost of SoC. Some people may question why not design one yourself? Because designing various ICs requires a lot of knowledge related to the IC, only a rich company like Apple has the budget to poach top engineers from well-known companies to design a brand new IC. Authorization through cooperation is better than doing it yourself. R&D is more cost-effective.

　　Compromise, SiP Introduces

　　As an alternative, SiP jumped onto the stage of integrated chips. Different from SoC, it purchases ICs from various companies and packages these ICs for the last time, thus eliminating the step of IP authorization and greatly reducing design costs. In addition, because they are independent ICs, the degree of mutual interference is greatly reduced.
　　
　　▲ Apple Watch uses SiP technology to package the entire computer architecture into a chip, which not only meets the expected performance but also reduces the size, allowing the watch to have more space for batteries. (Source: Apple official website)

　　The most famous product using SiP technology is the Apple Watch. Because the internal space of Watch is too small, it cannot adopt traditional technology, and the design cost of SoC is too high, so SiP has become the first choice. With SiP technology, not only can the size be reduced, but also the distance between each IC can be shortened, making it a feasible compromise solution. The figure below is the structure diagram of the Apple Watch chip, and you can see that quite a few ICs are included in it.
　　
　　▲ The internal configuration diagram of the S1 chip in the SiP package in the Apple Watch. (Source: chipworks)

　　After the packaging is completed, it is time to enter the testing stage. At this stage, it is necessary to confirm whether the packaged IC is operating normally. After it is correct, it can be shipped to the assembly plant to make the electronic products we see. So far, the semiconductor industry has completed the entire production task.

Top 10 IDM companies:

There are many Fabless (pure design, fabless) companies, such as:

Wafer Foundry Enterprises:

Packaging and testing factory:

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