Wafer bonding is distinguished by its name from wire bonding and die bonding used in traditional packaging. In Japanese, bonding is translated as bonding, which makes it easier to understand this process and process.

From the bonding way to classification, wafer bonding can be divided into permanent bonding and temporary bonding. As the name implies, permanent bonding does not require debonding, while temporary bonding also requires debonding, which reopens the joined wafers.

From the interface materials, it is divided into adhesive bonding with intermediate layer, eutectic bonding, metal hot pressing bonding, fusion bonding without intermediate layer and anode bonding.

Source: Wafer Bonding, Shawn Cunningham & Mario Kupnik, Chap.11

The purpose of bonding is also different, such as providing air-tight protection for the device, in certain application scenarios in MEMS and SAW; Another example is to provide mechanical support or layer transfer for thin wafers, such as IGBT and BSI applications are based on this purpose; At present, the latest and most important applications are the three-dimensional interconnection of crystal tubes, HBM, 3D NAND and the complementary field effect crystal tube CFET and back power supply network BPN under development. The recent rise of hybrid bonding (hybrid bonding) is aimed at this application process, the process because it contains both melt bonding and metal bonding characteristics named.

The early wafer bonding required little control of the engraving accuracy, and it could be within 10 microns after bonding. However, since the beginning of BSI, the nesting accuracy requirements have reached the level of 1.5 microns, and for 3D NAND and high-end BSI applications, it has reached the requirements of 300 nanometers or even 150 nanometers! With the development of bonding technology and the penetration of the forward process, the author boldly speculates that the precision requirements of tens of nanometers may be achieved in the future.

As mentioned earlier, the essence of bonding is bonding, which uses a variety of different physical and chemical methods to join the two interfaces, the principle has been discovered and applied long before humans cut the first wafer. Whether it is glue bonding with the aid of polymer compounds, eutectic bonding with the use of welding principles, or even melt bonding with the attraction of van der Waals forces between ultra-smooth surfaces, the basic principles of wafer bonding have been known for a long time before the birth of wafer bonding. However, the real large-scale industrial application of wafer bonding has only begun in the past ten years.

In 1969, Wallis and Pomerantz described using an electric field to bond silicon and soda glass wafers together at 500C, which we know today as anodic bonding.

In 1986, IBM and Toshiba found melt bonding. When silicon wafer is polished by mirror, it can attract each other to bond with each other even at room temperature without the help of other bonding media, which is also the beginning of silicon-silicon direct bonding. In the following years, melt bonding techniques for SOI,MEMS and III-V compounds were published one after another. After 1990s, plasma treated wafer surface bonding at room temperature + low temperature annealing and high vacuum without annealing melt bonding technology has been developed one after another.

In 2016, Sony produced image sensors using copper-silica hybrid bonding for the first time. This idea, which began in the mid-1980s, has finally become a reality after more than a decade of research and has been accepted by the industry.

Source: Handbook of Wafer Bonding, Chap.15

There are many ways to achieve three-dimensional interconnection by wafer bonding, but the fused bonding scheme in (a) and the hybrid bonding scheme in (d) above are more suitable for advanced CMOS processes.

Metal hot press bonding (c) requires the use of extremely high pressures (10-100 kN), and even high voltage electric fields such as anodic bonding, For the CMOS process compatibility is not so friendly, easy to destroy its previous metal pattern, so only need room temperature bonding + low temperature annealing melt bonding and hybrid bonding (d) because of its good process compatibility with CMOS, has been more and more favored.

Melting bonding is not born so mild, from the early need for 1000 ℃ high temperature annealing for several hours, to only need atmospheric pressure plasma surface activation after room temperature bonding, annealing at less than 400 ℃, and even in ultra-high vacuum plasma surface activation without annealing, which provides a guarantee for its strong CMOS process compatibility. Without the help of TSV, the interconnection distance between the upper and lower wafer is reduced to the shortest, and the electrical properties are further improved by using copper contact for hybrid bonding.

Thanks to the rapid development of melt bonding and hybrid bonding, the biggest obstacle to wafer bonding to CMOS interconnect technology has been removed.

Fusion bonding is usually a process of bonding with silicon-silicon or silicon-silicon dioxide as the bonding interface and after appropriate surface treatment. I have seen a saying that as long as the surface is smooth and flat enough, everything can bond, so indium phosphide and lithium niobate such special substrates can also be fused with silicon wafers!

A relatively well-known early application of melt bonding was the production of silicon on SOI insulators. As a substrate material with rich optical and electrical properties, the preparation of SOI is naturally more complicated than conventional silicon. Bare silicon wafers and thermal oxygen wafers are the main preparation methods of early SOI wafers, but due to their high cost, slow production speed and poor uniformity, their application scenarios are relatively limited. Since then, the SmartCut ® technology developed by France's Soitec has made a leap forward in cost, production speed and uniformity indicators. Bare silicon wafers as donor wafers after melt bonding, automatically fracture after hydrogen ion implantation, separate the donor wafers, and can be reused after surface polishing.

Source: Soitec官网

A more well-known application for melt bonding is the production of BSI backlit image transducers. In the initial stage, the BSI was fused to the CMOS wafer by the non-graphic wafer as the mechanical support, and then the CMOS backside was thinned to fabricate the pixel array. With the development of image processing, the image processing logic wafer and CMOS wafer are fused face to face, and connected by TSV. When the hybrid bonding technology matures, BSI has also entered the era of high-density interconnection, which is later.

Source: Status of the CMOS Image sensor Industry 2019, www.yole.fr

In addition, the author has also seen the use of melt bonding in some papers to interconnect microLED and MEMS chips with CMOS. In the CFET technology including IMEC, there are also applications using melt bonding to make three-dimensional crystal tubes. With the advent of the three-dimensional era of semiconductors, the potential of melt bonding is immeasurable.

When it comes to the most typical application of hybrid bonding, there is no doubt that the Xtacking ® stored in the Yangtze River. Through different processes, Memory wafer and CMOS wafer were fabricated one after another, and the contacts between them were constructed in the later process. Through hybrid bonding, these contacts are linked on, and Memory and CMOS are connected vertically.

Source: The New York Times

According to the Frauebhofer Institute, the advantages of hybrid bonding are three:

• Shorter interconnection distance: not only does it not need to connect with each other with leads, nor does it need to use TSV to cross the entire CMOS layer. It can be connected simply by connecting the copper contacts of the rear channel.

• Higher interconnect density: the area of copper contact is very small, compared to the diameter of 100 microns of tin ball and TSV, the copper contact in hybrid bonding process even less than 10 microns, no doubt can achieve higher interconnect density

• Lower cost: There is no doubt that it takes more time for each DIE to interconnect separately, and the large area and high density interconnect can be achieved through wafer bonding, which contributes to the improvement of production capacity by leaps and bounds! Naturally, production costs can also be reduced.

In addition to the BSI mentioned earlier, cases such as micro LED and CMOS mixed bonding also exist. In the latest research, there is even the practice that micro LED is cut into independent DIE and bonded to a 12-inch wafer for hybrid bonding and interconnection with CMOS 12-inch wafer after it is made on a small wafer. It can be seen that its process compatibility is very excellent. This is also another advantage of hybrid bonding, different technology nodes of CMOS can also be connected through copper contacts, the flexibility of process selection has also been improved by leaps and bounds!

Source: Integrating microLEDs with advanced CMOS, Compound Semiconductor, 2022

Of course, hybrid bonding is not perfect, such as failure DIE can not be known from the initial stage, only after the completion of integration, thinning and scribing and after passing the test can be distinguished, so the yield of the finished DIE will be greatly affected. Secondly, the bonding interface needs a high level up degree of flatness, and the internal stress of the wafer also needs to be controlled to reduce the wafer warpage. Compared with traditional packaging technology, the cleanliness level of ISO3 and above required for hybrid bonding is much higher than the cleanliness requirement of ISO5 in traditional sealing and testing plants, which puts high requirements on factory management and environmental control.

The realization of the process needs to rely on the support of materials and equipment, although it is the latter process, but the players are few and far between, Among them, Germany's Karl Suss and Austria's EVG (EV Group) come out on top, and Japan's Canon and Mitsubishi have special categories of bonding equipment, but neither market share nor technical level can be compared with these two top players. At present, the only systematic introduction of wafer bonding information is the "Wafer Bonding Manual," in which Seuss and EVG equipment in a very high rate of visibility, has been repeatedly mentioned, its popularity and leading position is self-evident.

SUSS and EVG have a high degree of product line overlap, and they cover almost all types of bonding processes at the same time. In addition to bonding machines, they also include alignment machines and double-sided lithography machines for wafer alignment, as well as measurement machines for detecting bonding accuracy. In the domestic bonding machine market, compared to EVG, SUSE has a better reputation and market share in universities and research institutes, but EVG in industrial applications is better. Especially the domestic advanced BSI production line, EVG's fully automatic melt bonder GeminiFB almost reached 100% market share!

At present, the domestic bonding machine is still mainly at the low end. Although the bonding machine developed by Shanghai S Company permeates the market of glue bonding and metal bonding, it has not yet entered the main position of melt bonding. And another domestic enterprise that specializes in bonding machine is H company, like S company, H company is a company known for photolithography subsystem, its 200nm alignment accuracy can not be compared with the previous generation of EVG products, but it is also a breakthrough for local enterprises! In addition, there are several semiconductor equipment manufacturing companies are developing new bonding equipment, after all, up to last year, the CIS industry has been growing for 10 years, the market space is quite broad! Although the CIS market fell for the first time in a decade in 2022, as demand for security and smart cities continues to grow, the CIS market is large enough to accommodate players other than Sus and EVG.

In the past decade, the pace of promoting Moore's Law has gradually slowed down, and more and more semiconductor companies are seeking advanced packaging to drive the improvement of chip performance. Heterogeneous integration is one of the solutions, and the wafer bonding process provides an efficient implementation path for it, becoming a strong candidate process!

When Intel and IMEC announce the future transistor development route in 2022 and enter the CFET era after 1nm, I believe that melt bonding and hybrid bonding will go from the back to the front, and highNA and hyperNA EUV lithography will lead the next 15 years of the semiconductor industry!

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